加拿大华人论坛 加拿大生活信息Opening: MSDG Digital Verification Lead

在加拿大

Please email me your resume at [email protected] if seriously interested.MSDG Digital Verification Lead - 1094110001About the Job:Division: MSDG Location: Burnaby, BC or Calgary, ABThe Mixed-Signal Design Group (MSDG) provides IP to various business units within PMC, including DSP-based SERDES, DDR PHYs, Flash PHYs, and FEC blocks. This IP usually involves both analog and digital components. The Digital Team within MSDG is responsible for the specification, design, verification, synthesis, and lab support of the digital portion of the IP.We are looking for an experienced digital verification engineer to drive improvements in our verification flow on future projects. This includes, but is not limited to, driving the transition from Specman to System Verilog, defining rigorous test methodologies, mentoring junior verification engineers, and evaluating 3rd party IP verification coverage.A successful candidate will be a leader with the vision, passion, and energy to drive great improvements in our group.Responsibilities:• Define and implement rigorous verification practices for MSDG digital IP• Drive the transition from Specman-based testbenches to System Verilog-based testbenches• Verification of complex subsystems• Mentor junior verification engineers• Define process to evaluate 3rd party IP verification coverage• Represent PMC at conferences and customer eventsMandatory Qualifications:• Education: advanced degree in EE (BASc, MASc, or PhD)• Work experience: 10+ years of ASIC development experience • Detailed knowledge of Specman, System Verilog, and other verification tools/languages• Proficiency with verification methodologies (UVM, OVM, etc)• Excellent written and oral communications skills• The ability to work autonomously• The ability to mentor junior engineers• The ability to work effectively with remote sitesOther Qualifications:The following qualifications are assets for the candidate, but not mandatory:• Experience with MSDG IP (Serdes, Flash, DDR, FEC)• Experience with all phases of digital design (specification, RTL coding, verification, synthesis, layout)• Experience with high speed timing (500MHz+)• Worked on a product that has shipped in significant quantity• Comfort within the Unix/Linux O/S• Experience with customer interaction and support

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