加拿大华人论坛 加拿大生活信息Looking for Senior Product Verification Engineer
在加拿大
有兴趣悄悄话。Vancouver 地区稳定职位Job DescriptionAbout the Job:Division: Enterprise Storage DivisionLocation: Burnaby (BC)Enterprise Storage Division is looking for a Product Verification Engineer to join the SAS/SATA verification team. This team is responsible for writing testbenches, testplans and coding functional coverage using UVM methodology.Responsibilities:• Develop, document, and execute verification test plans to verify complex digital integrated circuits at the block, subsystem or device level ( 100K to 10M+ gates), which are coded in System Verilog/Verilog/VHDL• Design, implement and maintain verification testbenches and bus-functional modes in Specman or System Verilog using best-in-class verification methodologies.• Write and execute testcases according to the verification test plans to verify these complex designs. Track down bugs and technical problems and work with the design team to ensure timely resolution.• Communicate regularly with the local and global design and verification resolve issues, communicate status and solve technical problems.• Read and understand applicable communication protocol standards.Qualifications:• Bachelor’s degree on Electrical Engineering or Computer Engineering• 4+ years related experience• Excellent analytical and debugging skills and the ability to proactively solve issues.• Excellent teamwork and time management skills and the ability to work under pressure.• Excellent verbal and written communication skills in English.• Experience using Verilog/VHDL is required and experience with using Specman/System Verilog is preferred.• Working knowledge with verification tools such as Cadence NC-Sim, waveform viewers, and other similar tools.• Working knowledge of ASIC design processes (design, verification, implementation, layout) and flows.• Knowledge of SAS/SATA protocols is an asset
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