加拿大华人论坛 加拿大百科Internal referral opportunity for ASIC verification engineers in Vancouver(big company)
在加拿大
Internal referral opportunity for ASIC verification engineers in Vancouver(big company)Minimum 3-year working experience on ASIC verification-Conferring with RTL Designers and SOC DV Leads on Verification Requirements and Methodologies-Writing/Implementing Test Plans and Strategy/Methodology Documents-Developing Testbenches and Verification Components such as UVCs, models, BFMs, and Re-usable Verification Environments-Writing, Modifying, and Maintaining Random and Directed Test Cases and Libraries in SystemVerilog/UVM-Analyzing Coverage Reports-Implementing Assertions and Functional Coverage-Utilizing In-House and 3rd Party IP/SOC CAD and EDA Tools for Design Verification-Deploying Industry-Leading Verification Methodologies such as UVM, and Formal Verification-Triaging and Debugging Regressions-Reproducing Functional Bugs found in Silicon in Simulation and/or Formal Verification toolsMSG me if you think you are qualified.
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